International Journal of Research Studies in Science, Engineering and Technology(IJRSSET)

IJRSSET Format

Volume - 2 Issue - 12

S.No	Title of the Article & Author(s)
1	Combining Spectral and Texture Information for Remote Sensing Image Segmentation M.Chaitanya, M.Haritha, P.Prasanna Murali Krishna View \| Download PDF \| Page No: 1-7
2	Reduction of Interference for Wireless Sensor Networks: A Regret Matching Based Approach Tangirala.Pratapa Reddy, M.V.Narashimha Reddy, P.Prasanna Murali Krishna View \| Download PDF \| Page No: 8-14
3	Implementation of Area Efficient IEEE-754 Double Precision Floating Point Arithmetic Unit Using Verilog Bhaskar Chittaluri View \| Download PDF \| Page No: 15-21
4	64 Bit Pipelined Hybrid Sparse Kogge-Stone Adder Using Different Valance Gangula Thirupathi Reddy, Dr. M. K Charan View \| Download PDF \| Page No: 22-28
5	Performance Enhancement of MIMO-MC-CDMA System by using Quasi-Orthogonal Space-Time Block Codes P. Sreesudha, Dr. B.L. Malleswari View \| Download PDF \| Page No: 29-31
6	Reduction of Leakage Power in Full Adder Circuit Using Power Gating Analysis Ankammarao Gudi Seva View \| Download PDF \| Page No: 32-37
7	Multiple Criteria Decision Making for Suppliers Evaluation: Using Analytic Network Process and VIKOR Approach Chun-Yan Jiang, Chun-Liang Lai, Chien-Hua Wang View \| Download PDF \| Page No: 38-44
8	An Analytical and Experimental Investigation of SCC Slab with Partial Replacement of Foundry Waste Sand T.Priyadharsini, Dr.R.Venkatasubramani, R.Elangovan View \| Download PDF \| Page No: 45-48

S.No	Title of the Article & Author(s)
1	Combining Spectral and Texture Information for Remote Sensing Image Segmentation M.Chaitanya, M.Haritha, P.Prasanna Murali Krishna View \| Download PDF \| Page No: 1-7
2	Reduction of Interference for Wireless Sensor Networks: A Regret Matching Based Approach Tangirala.Pratapa Reddy, M.V.Narashimha Reddy, P.Prasanna Murali Krishna View \| Download PDF \| Page No: 8-14
3	Implementation of Area Efficient IEEE-754 Double Precision Floating Point Arithmetic Unit Using Verilog Bhaskar Chittaluri View \| Download PDF \| Page No: 15-21
4	64 Bit Pipelined Hybrid Sparse Kogge-Stone Adder Using Different Valance Gangula Thirupathi Reddy, Dr. M. K Charan View \| Download PDF \| Page No: 22-28
5	Performance Enhancement of MIMO-MC-CDMA System by using Quasi-Orthogonal Space-Time Block Codes P. Sreesudha, Dr. B.L. Malleswari View \| Download PDF \| Page No: 29-31
6	Reduction of Leakage Power in Full Adder Circuit Using Power Gating Analysis Ankammarao Gudi Seva View \| Download PDF \| Page No: 32-37
7	Multiple Criteria Decision Making for Suppliers Evaluation: Using Analytic Network Process and VIKOR Approach Chun-Yan Jiang, Chun-Liang Lai, Chien-Hua Wang View \| Download PDF \| Page No: 38-44
8	An Analytical and Experimental Investigation of SCC Slab with Partial Replacement of Foundry Waste Sand T.Priyadharsini, Dr.R.Venkatasubramani, R.Elangovan View \| Download PDF \| Page No: 45-48